1. Field of the Invention
The present invention generally relates to computer science and, more specifically, to frame buffer access tracking via a sliding window in a unified virtual memory system.
2. Description of the Related Art
A typical computer system includes a central processing unit (CPU) and a parallel processing unit (PPU). Some PPUs are capable of very high performance using a relatively large number of small, parallel execution threads on dedicated programmable hardware processing units. The specialized design of such PPUs usually allows these PPUs to perform certain tasks, such as rendering 3-D scenes, much faster than a CPU. However, the specialized design of these PPUs also limits the types of tasks that the PPU can perform. By contrast, the CPU is typically a more general-purpose processing unit and therefore can perform most tasks. Consequently, the CPU usually executes the overall structure of a software application and then configures the PPU to implement tasks that are amenable to parallel processing.
As software applications execute on the computer system, the CPU and the PPU perform memory operations to store and retrieve data in physical memory locations. Some advanced computer systems implement a unified virtual memory architecture (UVM) common to both the CPU and the PPU. Among other things, the architecture enables the CPU and the PPU to access a physical memory location using a common (e.g., the same) virtual memory address, regardless of whether the physical memory location is within system memory or memory local to the PPU (PPU memory).
Typically, the PPU memory is relatively small, as compared to the CPU memory, and application programs reference more memory pages than the PPU memory is capable of storing. When the PPU memory is over-committed, the operating system (OS) selects memory pages to migrate from the PPU memory to the system memory in order to allow storage of newly-referenced memory pages. In some computer systems, an operating system (OS) randomly selects the memory pages to migrate. However, since the OS may select a memory page that is subsequently accessed by the PPU for migration, such an approach may reduce the performance of the PPU.
In another approach, the OS repurposes a previously-unused bit in each PPU page table entry (PTE) to track PPU memory pages that have been recently referenced. In operation, the OS temporarily turns off all access rights to a set of memory pages included in the PPU memory. If the PPU references a memory page included in this set of memory pages, then a page fault is generated. In response to the page fault, the OS restores access to the memory page and sets the PTE bit associated with accesses to the memory page to indicate that the memory page has recently been accessed. The OS preferentially selects memory pages that are not associated with a set access bit for migration from the PPU memory to the CPU memory.
While such an approach reduces the likelihood that the OS migrates memory pages that are subsequently accessed by the PPU, resolving the generated page faults degrades the overall performance of the computer system. Additionally, setting a bit in the PTE generally requires a read-modify-write operation on the PTE, which is a significant overhead, because the performance path in the PPU memory management unit (PPU MMU) performs only read operations. Further, if the PTE does not include any unused bits, this PTE-based approach allocates PPU memory for storing an access tracking bit for each memory page. Consequently, this approach undesirably reduces the amount of PPU memory available for storage of application program data.
As the foregoing illustrates, what is needed in the art is a more effective and efficient approach to tracking accesses to memory pages in a unified virtual memory architecture, especially to locate pages not recently referenced.